Semiconductor Device and Manufacturing Method Thereof

ABSTRACT

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese Patent ApplicationNo. JP 2008-276235 filed on Oct. 28, 2008, the content of which ishereby incorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor device and amanufacturing technique thereof, and in particular to a techniqueeffectively applied to a semiconductor device having wirings including amain conductive film containing copper as a main component.

BACKGROUND OF THE INVENTION

The buried wiring structure is formed by burying a wiring material in awiring opening such as a wiring trench or hole formed in an insulatingfilm with a wiring formation technique referred to as Damascenetechnique (Single-Damascene technique and Dual-Damascene technique).However, when a material of the main wiring is copper (Cu), Cu tends tobe diffused into an insulating film compared with a metal such asaluminum (Al). For this reason, in order to prevent the buried wiringmade of copper from directly making contact with the insulating film,the surface (bottom and side surfaces) of the buried wiring is coveredwith a thin barrier metal film, thereby suppressing or preventing copperin the buried wiring from being diffused into the insulating film. Also,a barrier insulating film as a wiring cap made of, for example, asilicon nitride film is formed on an upper surface of the insulatingfilm having a wiring opening formed therein to cover the upper surfaceof the buried wiring, thereby suppressing or preventing copper in theburied wiring from being diffused from the upper surface of the buriedwiring into the insulating film.

In recent years, intervals between the buried wirings have beendecreased with the increase in integration degree of a semiconductordevice. This increases parasite capacitance between wirings to cause asignal delay, so that cross talk occurs between adjacent wirings. Forthis reason, it is desired to reduce the parasite capacitance betweenwirings. For the reduction of the parasite capacitance between wirings,a low dielectric-constant material is used for an inter-wiringinsulating film. Meanwhile, for example, Japanese Patent ApplicationLaid-Open Publication No. 2003-297918 (Patent Document 1) discloses atechnique of forming each wiring in a tapered shape and also forming anair gap between these wirings. By means of this air gap, inter-wiringcapacitance is reduced. Also, in Japanese Patent Application Laid-OpenPublication No. 2006-120988 (Patent Document 2), the inter-layerinsulating film is etched deeper than the bottom of the wirings tofurther reduce the capacitance.

SUMMARY OF THE INVENTION

However, the result of studies by the inventor has found that thefollowing problems arise in the above-mentioned buried wiring techniqueusing copper as a main conductive layer.

Patent Document 1 shows that the capacitance is reduced by adopting anair-gap structure, compared with a normal Damascene structure. However,according to the studies by the inventor, in a conventional structuredepicted in (a) of FIG. 1 where a barrier insulating film is present onthe bottom of an air gap, it is difficult to achieve an effectivedielectric constant presented in International Technology Roadmap forSemiconductors (ITRS) in the next generation of 32 nm nodes onward. Bycontrast, according to the studies by the inventor, in a structureaccording to the present invention depicted in (b) of FIG. 1, that is,in a structure where no barrier insulating film is present on the bottomof the air gap, a capacitance reduction effect of approximately 12% to13% is obtained by removing just a slight barrier insulating film, sothat an effective dielectric constant desired for 32 nm nodes onward canbe achieved.

Patent Document 2 discloses an example where an inter-wiring insulatingfilm is formed deeper than the bottom of a trench. In Patent Document 2,however, no consideration is given to the measures for reducingcapacitance variations. Depth variations become more conspicuous as theetching becomes deeper, and it causes an increase in capacitancevariations. In the present invention, a through-hole interlayerinsulating film made of a material different from that of theinter-wiring insulating film is formed at a depth-direction position inwhich the air gap is desired to be formed, and etching for the removalof the inter-wiring insulating film is stopped by a via interlayerinsulating film. By this means, the capacitance variations can be morereduced compared with the conventional structure.

An object of the present invention is to provide a semiconductor devicecapable of reducing capacitance between wirings having a main conductivelayer made of copper, and a manufacturing method of the semiconductordevice.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of this specificationand the accompanying drawings.

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

A manufacturing method of a semiconductor device according to thepresent invention includes the following steps of:

(a) forming a plurality of wiring trenches in a first insulating film ona semiconductor substrate;

(b) forming a first conductive film on the first insulating filmincluding respective insides of the plurality of wiring trenches;

(c) forming wirings formed of the first conductive film inside therespective wiring trenches by removing a portion of the first conductivefilm outside the wiring trenches by CMP;

(d) forming a first barrier insulating film on the first insulating filmand the wirings;

(e) forming a reservoir position by removing the first barrierinsulating film and the first insulating film except portions of thefirst barrier insulating film and the first insulating film in lowerregions and their peripheral regions of through holes, which are formedlater and from which upper surfaces of the wirings are exposed;

(f) forming a second barrier insulating film on the first barrierinsulating film and side and upper surfaces of the wirings so that thesecond barrier insulating film on spaces between the wirings is madethinner than the second barrier insulating film on the wirings;

(g) forming a second insulating film on the second barrier insulatingfilm while leaving gaps in space regions between the wirings from whichthe first barrier insulating film and the first insulating film havebeen removed;

(h) forming through holes penetrating through the first barrierinsulating film, the second barrier insulating film and the secondinsulating film on an upper portion of the wirings; and

(i) forming a second conductive film inside the through holes.

Another manufacturing method of a semiconductor device according to thepresent invention includes the following steps of:

(a′) forming a plurality of wiring trenches in a first insulating filmand a second insulating film on a semiconductor substrate;

(b′) forming a first conductive film on the second insulating filmincluding respective insides of the plurality of wiring trenches;

(c′) forming wirings formed of the first conductive film inside therespective wiring trenches by removing a portion of the first conductivefilm outside the wiring trenches by CMP;

(d′) forming a first barrier insulating film on the second insulatingfilm and the wirings;

(e′) forming a reservoir position by removing the first barrierinsulating film and the second insulating film except portions of thefirst barrier insulating film and the second insulating film in lowerregions and their peripheral regions of through holes, which are formedlater and from which upper surfaces of the wirings are exposed;

(f) forming a second barrier insulating film on the first barrierinsulating film and side and upper surfaces of the wirings so that thesecond barrier insulating film on spaces between the wirings is madethinner than the second barrier insulating film on the wirings;

(g′) forming a third insulating film on the second barrier insulatingfilm while leaving gaps in space regions between the wirings from whichthe first barrier insulating film and the second insulating film havebeen removed;

(h′) forming through holes penetrating through the first barrierinsulating film, the second barrier insulating film and the thirdinsulating film on an upper portion of the wirings; and

(i) forming a second conductive film inside the through holes.

In the above, the combined structure of the first insulating film andthe second insulating film is characterized by having high selectivityin dry etching. By this means, when the second insulating film isremoved after forming wirings, the first insulating film serves as astopper film, and a shape with the uniform etching depth can beobtained. Therefore, an air-gap shape formed thereafter has a similarstructure, and air-gap wirings with less capacitance variations can beformed.

The effects obtained by typical embodiments of the inventions disclosedin this application will be briefly described below.

Compared with the conventional air-gap structure, the capacitance andcapacitance variations can be further reduced.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a diagram depicting an effective dielectric-constant reductioneffect when an embodiment of the present invention is used;

FIG. 2 is a plan view of principal parts in the manufacturing process ofa semiconductor device according to an embodiment of the presentinvention;

FIG. 3 is a cross-sectional view of an A-A line in FIG. 2;

FIG. 4 is a cross-sectional view of principal parts in the manufacturingprocess of a semiconductor device continued from FIG. 3;

FIG. 5 is a cross-sectional view of principal parts in the manufacturingprocess of a semiconductor device continued from FIG. 4;

FIG. 6 is a cross-sectional view of principal parts in the manufacturingprocess of a semiconductor device continued from FIG. 5;

FIG. 7 is a plan view of principal parts in a region corresponding toFIG. 6;

FIG. 8 is a cross-sectional view of an A-A line in FIG. 7 continued fromFIG. 7;

FIG. 9A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 8;

FIG. 9B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 8;

FIG. 10A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 9A;

FIG. 10B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 9B;

FIG. 11A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 10A;

FIG. 11B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 10B;

FIG. 12 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 7;

FIG. 13 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 12;

FIG. 14 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 13;

FIG. 15A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 14;

FIG. 15B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 14;

FIG. 16A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 15A;

FIG. 16B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 15B;

FIG. 17A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 14;

FIG. 17B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 14;

FIG. 18A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 17A;

FIG. 18B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 17B;

FIG. 19 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIGS. 11and 16;

FIG. 20 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 19;

FIG. 21 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 20;

FIG. 22 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 21;

FIG. 23 is a plan view of principal parts in a region corresponding toFIG. 2 in the manufacturing process of a semiconductor device continuedfrom FIG. 22;

FIG. 24 is a cross-sectional view of an A-A line in FIG. 23 continuedfrom FIG. 23;

FIG. 25 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 24;

FIG. 26 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 25;

FIG. 27 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 26;

FIG. 28 is a plan view of principal parts in a region corresponding toFIG. 2 in the manufacturing process of a semiconductor device continuedfrom FIG. 27;

FIG. 29 is a cross-sectional view of an A-A line in FIG. 28 continuedfrom FIG. 28;

FIG. 30 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 29;

FIG. 31 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 30;

FIG. 32 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention;

FIG. 33A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 3;

FIG. 33B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 3;

FIG. 34A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 33A;

FIG. 34B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 33B;

FIG. 35A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 34A;

FIG. 35B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 34B;

FIG. 36 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 35;

FIG. 37A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 36;

FIG. 37B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 36;

FIG. 38A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 37A;

FIG. 38B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 37B;

FIG. 39 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 38;

FIG. 40A is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 39;

FIG. 40B is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device continued from FIG. 39;and

FIG. 41 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference numbersthroughout the drawings for describing the embodiments, and therepetitive description thereof will be omitted. In addition, thedescription of the same or similar portions is not repeated in principleunless particularly required in the following embodiments.

First Embodiment

A semiconductor device and a manufacturing method thereof according to afirst embodiment will be described with reference to the drawings. FIG.2 is a plan view of principal parts in the manufacturing process of asemiconductor device, for example, Complementary Metal InsulatorSemiconductor Field Effect Transistor (CMISFET) according to anembodiment of the present invention. FIG. 3 is a cross-sectional view ofan A-A line in FIG. 2. As depicted in FIGS. 2 and 3, a wafer orsemiconductor substrate 1 made of p-type monocrystalline silicon havinga resistivity of, for example, 1 Ωcm to 10 Ωcm has isolation regions 2formed on its main surface. The isolation regions 2 are made of siliconoxide or the like and are formed by, for example, Shallow TrenchIsolation (STI) or LOCOS (Local Oxidization of Silicon).

The semiconductor substrate 1 has a p-type well 3 and an n-type well 4formed from its main surface to a predetermined depth. The p-type well 3is formed by, for example, ion-implanting impurities such as boron, andthe n-type well 4 is formed by, for example, ion-implanting impuritiessuch as phosphorus.

In the region of the p-type well 3, an n-channel MISFET (Qn) is formedin an active region surrounded by the isolation regions 2. Also, in theregion of the n-type well 4, a p-channel MISFET (Qp) is formed in anactive region surrounded by the isolation regions 2. Gate insulatingfilms 5 of the n-type MISFET (Qn) and the p-type MISFET (Qp) are formedof, for example, a thin silicon oxide film or silicon oxynitride film,and are formed by, for example, thermal oxidation.

Gate electrodes 6 of the n-type MISFET (Qn) and the p-type MISFET (Qp)are formed by stacking, for example, a titanium silicide (TiSi_(x))layer or cobalt silicide (CoSi_(x)) layer 10 on a low-resistancepolycrystalline silicon film. A side-wall spacer or side wall 7 made of,for example, silicon oxide is formed on the side wall of the gateelectrode 6.

Also, n-type semiconductor regions 8 which are source and drain regionsof the n-type MISFET (Qn) are formed by ion-implanting impurities suchas phosphorus into both side regions of the gate electrode 6 and theside wall 7 of the p-type well 3 after the formation of the side wall 7.Then, p-type semiconductor regions 9 which are source and drain regionsof the p-type MISFET (Qp) are formed by ion-implanting impurities suchas boron into both side regions of the gate electrode 6 and the sidewall 7 of the n-type well 4 after the formation of the side wall 7.Further, on a part of the upper surface of the n-type semiconductorregion 8 and the p-type semiconductor region 9, a silicide layer 10 suchas a titanium silicide layer or a cobalt silicide layer is formed.

On the above-described semiconductor substrate 1, a silicon nitride film11 is formed so as to cover the gate electrode 6 and the side wall 7.Also, an insulating film 12 formed thereon is made of an insulating filmwith high reflow properties such as a Boron-doped Phospho Silicate Glass(BPSG) film capable of filling narrow spaces between the gate electrodes6. In the insulating film 12, contact holes 13 are formed. At the bottomof the contact holes 13, a part of a main surface of the semiconductorsubstrate 1, for example, a part of the n-type semiconductor region 8, apart of the p-type semiconductor region 9, and a part of the gateelectrode 6 is exposed.

In each of these contact holes 13, a conductive film made of tungsten(W) or the like is formed. The conductive film is formed by, forexample, forming a titanium nitride film, forming a tungsten film on thetitanium nitride film by Chemical Vapor Deposition (CVD) so as to fillthe contact holes 13, and then removing unnecessary portions of thetungsten film and the titanium nitride film on the insulating film 12 byChemical Mechanical Polishing (CMP) or etch-back.

On the insulating film 12 having the contact holes 13 embedded therein,first layer wirings 15 are formed by the Damascene technique in which,after trenches are formed in an interlayer insulating film formed of,for example, an insulating film 14 a and an insulating film 14 b, thetrenches are each filled with a conductive film made of tungsten or thelike and then an excess of the conductive film is removed by CMP. Thefirst layer wirings 15 are electrically connected via the contact holes13 to the semiconductor regions 8 and 9 for sources and drains and thegate electrodes 6 of the n-type MISFET (Qn) and the p-type MISFET (Qp).The first layer wirings 15 are not limited to tungsten and variousmodifications can be made therein. For example, the first layer wirings15 may be made of a single-element film of any one of aluminum (Al) andaluminum alloy or a stacked metal film obtained by forming a metal filmmade of titanium (Ti), titanium nitride (TiN) or the like on at leastone of upper and lower layers of the single-element film.

When a trench is processed by the Damascene technique, the insulatingfilm 14 a serves as an etching stopper film, so that the resistancevariations can be reduced. For example, a silicon nitride (Si_(x)N_(y))film, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) filmmay be used as the insulating film 14 a. The silicon nitride film,silicon carbide film or silicon carbonitride film can be formed by, forexample, plasma CVD. An example of the silicon carbide film formed byplasma CVD is BLOk (manufactured by AMAT, relative permittivity=4.3 to5.0). In its formation, mixed gas of trimethylsilane and helium (or N₂,NH₃) is used.

For the insulating film 14 b, a silicon oxide film (for example,Tetraethoxysilane (TEOS) oxide film) is used. Furthermore, for thereduction of the inter-wiring capacitance, the insulating film 14 b ismade of, for example, a low dielectric-constant material (so-calledLow-K insulating film or Low-K material) such as organic polymer ororganic silica glass. An example of the low dielectric-constantinsulating film (Low-K insulating film) can be an insulating film with adielectric constant lower than the dielectric constant of a siliconoxide film (for example, TEOS oxide film) included in a passivationfilm. In general, an insulating film with a dielectric constantapproximately equal to or lower than the dielectric constant of the TEOSoxide film ε=4.1 to 4.2 is called a low dielectric-constant insulatingfilm.

Examples of the organic polymer as the low dielectric-constant materialinclude SiLK (manufactured by The Dow Chemical Co., relativepermittivity=2.7, heatproof temperature=490° C. or higher, dielectricbreakdown withstand voltage=4.0 to 5.0 MV/Vm) and FLARE of a polyallylether (PAE) material (manufactured by Honeywell Electronic MaterialsCo., relative permittivity=2.8, heatproof temperature=400° C. orhigher). This PAE material has features of offering high basicperformance, excellent mechanical strength and thermal stability, andexcellent cost effectiveness. Examples of the organic silica glass (SiOCmaterials) as a low dielectric-constant material include HSG-R7(manufactured by Hitachi Chemical Co. Ltd., relative permittivity=2.8,heatproof temperature=650° C.), Black Diamond (manufactured by AppliedMaterials, Inc. of USA, relative permittivity=3.0 to 2.4, heatprooftemperature=450° C.), and p-MTES (manufactured by Hitachi Kaihatsu,relative permittivity=3.2). Other SiOC materials include, for example,CORAL (manufactured by Novellus Systems, Inc. of USA, relativepermittivity=2.7 to 2.4, heatproof temperature=500° C.) and Aurora 2.7(manufactured by ASM Japan K. K., relative permittivity=2.7, heatprooftemperature=450° C.).

Further, for example, an FSG (SiOF-based material), HSQ (hydrogensilsesquioxane) material, MSQ (methyl silsesquioxane) material, porousHSQ material, porous MSQ material, or porous organic material may alsobe used as a low dielectric-constant material of the insulating film 14b. Examples of the HSQ material include OCD T-12 (manufactured by TokyoOhka Kogyo Co., Ltd., relative permittivity=3.4 to 2.9, heatprooftemperature=450° C.), FOx (manufactured by Dow Corning Corp., relativepermittivity=2.9), and OCL T-32 (manufactured by Tokyo Ohka Kogyo Co.,Ltd., relative permittivity=2.5, heatproof temperature=450° C.).Examples of the MSQ material include OCD T-9 (manufactured by Tokyo OhkaKogyo Co., Ltd., relative permittivity=2.7, heatproof temperature=600°C.), LKD-T200 (manufactured by JSR Co., relative permittivity=2.7 to2.5, heatproof temperature=450° C.), HOSP (manufactured by HoneywellElectronic Materials, relative permittivity=2.5, heatprooftemperature=550° C.), HSG-RZ25 (manufactured by Hitachi Chemical Co.,Ltd., relative permittivity=2.5, heatproof temperature=650° C.), OCLT-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relativepermittivity=2.3, heatproof temperature-500° C.), and LKD-T400(manufactured by JSR Co., relative permittivity=2.2 to 2, heatprooftemperature 450° C.).

Examples of the porous HSQ material include XLK (manufactured by DowCorning Corp. of USA, relative permittivity=2.5 to 2), OCL T-72(manufactured by Tokyo Ohka Kogyo Co., relative permittivity=2.2 to 1.9,heatproof temperature=450° C.), Nanoglass (manufactured by HoneywellElectronic Materials, relative permittivity=2.2 to 1.8, heatprooftemperature=500° C. or higher), and MesoELK (manufactured by AirProducts and Chemicals, Inc., relative permittivity=2 or lower).Examples of the porous MSQ material include HSG-6211X (manufactured byHitachi Chemical Co., Ltd., relative permittivity=2.4, heatprooftemperature=650° C.), ALCAP-S (manufactured by Asahi Kasei Corporation,relative permittivity=2.3 to 1.8, heatproof temperature=450° C.),OCLT-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relativepermittivity=2.2 to 1.9, heatproof temperature=600° C.), HSG-6210X(manufactured by Hitachi Chemical Co., Ltd., relative permittivity=2.1,heatproof temperature=650° C.), and silica aerogel (manufactured by KobeSteel Ltd., relative permittivity=1.4 to 1.1). Examples of the porousorganic material include PolyELK (manufactured Air Products andChemicals, Inc., relative permittivity=2 or smaller, heatprooftemperature=490° C.). The SiOC and SiOF materials described above areformed by, for example, CVD. By way of example, Black Diamond describedabove is formed by CVD using mixed gas of trimethylsilane and oxygen.Also, the p-MTES described above is formed by, for example, CVD usingmixed gas of methyltriethoxysilane and N₂O. Other lowdielectric-constant insulating materials are formed by, for example, thecoating method.

When such a Low-K material is used, an insulating film as a Low-K cap isrequired in some cases on the insulating film 14 b. For the insulatingfilm as a Low-K cap, for example, a silicon oxide (SiO_(x)) filmtypified by silicon dioxide (SiO₂) or a pSiOC film with a relativelyhigh film strength is used. Such a Low-K cap film has functions of, forexample, ensuring mechanical strength of the insulating film 14 b,protecting the surface, and ensuring resistance to moisture in the CMPprocess.

On the first layer wirings 15, an inter-through-hole-layer structuremade of insulating films 16 and 17 is provided, and the insulating films16 and 17 can be fabricated using the same method and material as thoseof the insulating films 14 a and 14 b in the same manner as thefabrication of the first layer wirings 15. In these insulating films 16and 17, via or through holes 18 from which a part of the first layerwirings 15 is exposed are formed. These through holes 18 are each filledwith a conductive film made of, for example, tungsten.

FIGS. 4 to 6 are cross-sectional views of principal parts in themanufacturing process of a semiconductor device continued from FIG. 2.In FIGS. 4 to 6, for easy understanding, the illustration of portionscorresponding to the structure below the insulating film 17 in FIG. 3 isomitted.

First, in the present embodiment, as depicted in FIG. 4, an insulatingfilm 20 is formed by plasma CVD or the like on the insulating film 17having the through holes 18 embedded therein. The insulating film 20 ismade of a silicon nitride film formed by, for example, plasma CVD, andhas a thickness of, for example, approximately 25 nm to 50 nm. Asanother material for the insulating film 20, a single-element film ofany one of a silicon carbide film formed by, for example, plasma CVD, anSiCN film formed by plasma CVD, and a silicon oxynitride (SiON) filmformed by plasma CVD may be used. When any of these films is used, thedielectric constant can be significantly reduced compared with a siliconnitride film, and therefore, wiring capacitance can be reduced, and theoperation speed of the semiconductor device can be improved. An exampleof the silicon carbide film formed by plasma CVD is BLOk (manufacturedby AMAT). Also, for the formation of an SiCN film, for example, mixedgas of helium (He), ammonium (NH₃) and trimethylsilane (3MS) is used.Also, an example of the silicon oxynitride film formed by plasma CVD isPE-TMS (manufactured by Canon, relative permittivity=3.9), and for theformation thereof, for example, mixed gas of trimethoxysilane (TMS) gasand nitrogen oxide (N₂O) gas is used.

Next, an insulating film 21 is formed on the insulating film 20. As theinsulating film 21, a Low-K insulating film made of the above-describedLow-K material, that is, an SiOF film or an SiOC film is used. Also, foran insulating film 22 formed to be a cap on the insulating film 21, forexample, a silicon oxide film is used. Alternatively, for thesimplification of the process, a single-element film of silicon oxide orSiOC can be used for the insulating film 21 by omitting the insulatingfilm 22.

Next, a reflection preventive film 23 and a photo-resist film aresequentially formed on the insulating film 22, and the photo-resist filmis patterned by exposure to form a photo-resist pattern 24. Then, by thedry-etching using the photo-resist pattern 24 as an etching mask, thereflection preventive film 23 is selectively removed. Thereafter, by thedry-etching using the photo-resist pattern 24 as an etching mask, theinsulating films 22 and 21 are selectively removed to form openings.Then, ashing is performed to remove the photo-resist pattern 24 and thereflection preventive film 23, and finally, the insulating film 20exposed from the openings of the insulating films 22 and 21 are etched.In this manner, as depicted in FIG. 5, openings or wiring trenches 25are formed. From the bottom surfaces of the wiring trenches 25, theupper surfaces of the plugs (through holes) 18 are exposed.Alternatively, it is also possible to selectively remove the insulatingfilms 20, 21 and 22 by the dry-etching using the photo-resist pattern 24as an etching mask to form the openings or wiring trenches 25, and then,remove the photo-resist pattern 24 and the reflection preventive film23.

Next, as depicted in FIG. 6, a thin conductive barrier film (firstconductive film) 26 a having a thickness of approximately 5 nm to 50 nmand made of, for example, titanium nitride (TiN) is formed over theentire main surface of the substrate 1 by using sputtering. Theconductive barrier film 26 a has functions of, for example, preventingthe diffusion of copper for forming a main conductive film describedfurther below and improving wettability of copper at the time of reflowof the main conductive film. As a material for the conductive barrierfilm 26 a, a high-melting metal nitride such as tungsten nitride (WN) ortantalum nitride (TaN) which hardly reacts with copper can be used inplace of titanium nitride. Also, as a material for the conductivebarrier film 26 a, a material obtained by adding silicon (Si) to ahigh-melting metal nitride, a high-melting metal unlikely to react withcopper such as tantalum (Ta), titanium (Ti), tungsten (W) or titaniumtungsten (TiW) alloy, and a TaN/Ta stacked barrier obtained by combiningTaN with high adhesion to an insulating film and Ta with high Cuwettability can be used.

Subsequently, a relatively-thick main conductive film (second conductivefilm) 26 b having a thickness of, for example, approximately 800 nm to1600 nm and made of copper is formed on the conductive barrier film 26a. The main conductive film 26 b can be formed by using, for example,CVD, sputtering, or plating. Thereafter, the substrate 1 is subjected toa heat treatment in a non-oxidation atmosphere (for example, hydrogenatmosphere or nitrogen atmosphere) at, for example, approximately 150 to400° C. to reflow the main conductive film 26 b, thereby tightly fillingthe wiring trenches 25 with copper.

Next, the main conductive film 26 b and the conductive barrier film 26 aare polished by CMP. By this means, as depicted in FIG. 6, second layerwirings (wirings) 26 formed of the relatively-thin conductive barrierfilm 26 a and the relatively-thick main conductive film 26 b are formedin the wiring trenches 25. These second layer wirings 26 areelectrically connected to the first layer wirings 15 via the plugs 18.

FIG. 7 is a plan view of principal parts in a region corresponding toFIG. 6. FIG. 7 depicts the second layer wirings 26 and a formationposition 27 of a through hole connected to the second layer wiring 26and an upper layer thereof. When this through hole position ismisaligned by an exposing apparatus in a lithography process and a gap(air gap) is present at a lower portion of the through hole, cleaningsolution and Cu plating solution penetrate through thereafter, so thatproblems such as electrical connection failure and capacitance increaseare caused. Therefore, as the measures for the misaligned through hole(misalignment of the through hole), a reservoir formation position 28has to be set so that a reservoir of an insulating film is present atthe bottom of the via to attain a normal interlayer structure even whenmisalignment occurs. Reservoir formation methods will be described withreference to FIG. 8 and subsequent figures.

FIG. 8 is a cross-sectional view of an A-A line in FIG. 7 continued fromFIG. 7. Also in FIG. 8, the illustration of portions corresponding tothe structure below the insulating film 17 in FIG. 3 is omitted. Abarrier insulating film 29 having a thickness of 20 nm to 50 nm isformed on the insulating film 22 and the second layer wirings 26. Thebarrier insulating film 29 is made of, for example, a silicon nitridefilm, and it functions as a barrier insulating film for copper wirings.Therefore, the barrier insulating film 29 suppresses or prevents copperin the main conductive film 26 b in each second layer wiring 26 frombeing diffused into an interlayer insulating film 36 formed later. Asanother material for the barrier insulating film 29, for example, asingle-element film of any one of a silicon carbide (SiC) film, asilicon carbonitride (SiCN) film, and a silicon oxynitride (SiON) filmmay be used. When any of these films is used, the dielectric constantcan be significantly reduced compared with a silicon nitride film, andtherefore, wiring capacitance can be reduced, and the operation speed ofthe semiconductor device can be improved. An example of the siliconcarbide film formed by plasma CVD is BLOk (manufactured by AMAT), andits film formation gas is as described above. For the formation of theSiCN film, for example, mixed gas of helium (He), ammonium (NH₃) andtrimethylsilane (3MS) is used. Also, an example of the siliconoxynitride film formed by plasma CVD is PE-TMS (manufactured by Canon,relative permittivity=3.9). For the formation of the silicon oxynitridefilm, for example, mixed gas of trimethoxysilane (TMS) gas and nitrogenoxide (N₂O) gas is used.

Thereafter, photo-resist films are sequentially formed on the barrierinsulating film 29, and the photo-resist films are patterned by exposureto form a photo-resist pattern 30. At this time, the barrier insulatingfilm 29 functions as a reflection preventive film for the photo-resistpattern 30 and the copper wirings 26. At the time of the formation ofsuch a reservoir layer, in order to further increase the accuracy, areflection preventive film can be used at the bottom of the photo-resistfilm and on an upper portion of the barrier insulating film 29. Asdescribed above, the structure in which at least one insulating filmlayer is inserted between the photo-resist pattern for reservoir and thelower wirings is important.

Then, by the dry-etching using the photo-resist pattern 30 as an etchingmask, the insulating films 29, 22, 21 and 20 are selectively removed toform openings (FIG. 9A). At this time, the semiconductor substrate 1 isplaced in a process chamber of a plasma CVD apparatus, and CF₄ gas isintroduced to apply plasma power supply, thereby performing the CF₄plasma process to the substrate 1 (in particular, CMP surface where thesecond layer wirings 26 are exposed) and removing the insulating films29, 22, 21 and 20. After the CF₄ plasma process, an organic byproductand a fluorinated byproduct are temporarily and slightly produced on theCu wiring surface of the film 26 b, but they can be removed bypost-cleaning performed thereafter (for example, organic-acid cleaning,hydrofluoric acid cleaning, organic alkaline cleaning, or cleaning witha mixed fluid thereof) or by a hydrogen annealing process. Also, when anorganic film containing no silicon such as SiLK is used as theinsulating film 21, reducing plasma such as ammonium or N2/H2 mixed gasis used for the etching of the insulating film 21. Here, the plasmaprocess indicates a process in which a surface of a substrate or asurface of a member when a member such as an insulating film or a metalfilm is formed on the substrate is exposed to an environment in a plasmastate and the surface is processed by providing a chemical andmechanical (bombardment) effect of the plasma onto the surface. Also,plasma in a reducing atmosphere indicates a plasma environment in whichreactive species such as radicals, ions, atoms and molecules having areducing effect, that is, an effect of drawing oxygen are dominantlypresent. Furthermore, for the reduction of wiring capacitance more thanFIG. 9A, the structure in which the insulating film 17 is removed moredeeply than the bottom of the wirings can be formed as depicted in FIG.9B.

FIGS. 10A and 10B are cross-sectional views of principal parts in themanufacturing process of a semiconductor device continued from FIGS. 9Aand 9B, respectively. Also in FIGS. 10A and 10B, the illustration of theportions corresponding to the structure below the insulating film 17 inFIG. 3 is omitted. After the insulating films 22, 21 and 20 are removed,post-cleaning and hydrogen annealing process are performed, and then, aninsulating film 31 is formed over the entire main surface of thesemiconductor substrate 1 by plasma CVD or the like. More specifically,the insulating film 31 with a thickness of 20 nm to 50 nm is formed soas to cover the upper surface and side surface of each of the secondlayer wirings 26, the barrier insulating film 29 for use in theformation of the reservoir, and the insulating film 17. At this time,the insulating film 31 is formed under the condition that the insulatingfilm 31 is not formed in a conformal manner in a space between nearestwirings (minimum space between adjacent wirings or minimum pitch betweenwirings). Here, the nearest wirings correspond to the adjacent wiringshaving the minimum space therebetween in the wirings of the same layer(distance between adjacent wirings). In the space between nearestwirings, the reduction in parasite capacitance is more important.

In the space between nearest wirings, as the deposition of theinsulating film 31 proceeds, the reactive species is obstructed by adeposited matter near an upper portion of the side surfaces of thefacing wirings (facing surfaces of wirings), and gradually becomesdifficult to enter a lower portion thereof. For this reason, thedeposition rate near the lower portion of the side surfaces of thefacing wirings is lower than the deposition rate near the upper portionthereof. Therefore, the thickness of the insulating film 31 deposited onthe side surfaces of the facing wirings is not uniform, and thethickness near the upper portion is larger than the thickness near thelower portion. This phenomenon is more conspicuous in a space betweennearest wirings among the second layer wirings 26. Therefore, it is mosteffective for the capacitance reduction to prevent the insulating film31 from being formed on the bottom of the space between nearest wirings.However, it is still effective for the capacitance reduction to form theinsulating film 31 so that coverage on the space between nearest wiringsis equal to or lower than approximately 80% with respect to thethickness of the insulating film 31 on the second layer wirings 26 asdepicted in FIGS. 11A and 11B.

The insulating film 31 is made of, for example, a silicon nitride film,and it functions as a barrier insulating film for copper wirings.Therefore, the insulating film 31 suppresses or prevents copper in themain conductive film 26 b of each of the second layer wirings 26 frombeing diffused into the interlayer insulating film 36 formed later. Asanother material for the insulating film 31, a single-element film ofany one of a silicon carbide (SiC) film, a silicon carbonitride (SiCN)film, and a silicon oxynitride (SiON) film may be used. When any ofthese films is used, the dielectric constant can be significantlyreduced compared with a silicon nitride film, and therefore, the wiringcapacitance can be reduced and the operation speed of the semiconductordevice can be improved. An example of the silicon carbide film formed byplasma CVD is BLOk (manufactured by AMAT), and its film formation gas isas described above. For the formation of the SiCN film, for example,mixed gas of helium (He), ammonium (NH₃) and trimethylsilane (3MS) isused. Also, an example of the silicon oxynitride film formed by plasmaCVD is PE-TMS (manufactured by Canon, relative permittivity=3.9). Forthe formation of the silicon oxynitride film, for example, mixed gas oftrimethoxysilane (TMS) gas and nitrogen oxide (N₂O) gas is used.

As depicted in FIGS. 10 and 11, in the wiring structure fabricated asdescribed above, the barrier insulating film in a region where throughholes are fabricated has a thickness relatively larger than that of anupper portion of the wirings where no through hole is formed. Since thebarrier insulating film on a lower portion of the through holes servesalso as an etching stopper layer at the time of processing the throughholes, its thickness has to be at least approximately 40 nm to 50 nm.Therefore, for example, if the barrier insulating films 29 and 31 eachhaving a thickness of 25 nm are formed, the barrier insulating film inthe reservoir region where a through hole may be present has a thicknessof 50 nm, and in other regions around the wirings, the thickness is only25 nm, which is the thickness of the barrier insulating film 31. In thismanner, it is possible to efficiently reduce the capacitance and ensurea margin in the processing of the through holes.

Next, a reservoir formation method different from that described abovewith reference to FIGS. 8 to 11 will be described with reference toFIGS. 12 to 18.

FIG. 12 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to anotherembodiment of the present invention continued from FIG. 7. In thethrough-hole reservoir formation method described above with referenceto FIGS. 8 to 11, due to the etching using the photo-resist pattern 30,a Cu residual film may occur around the barrier insulating film 29 andthe second layer wiring 26 depending on the dry-etching apparatus. Toget around this, a method of forming a reservoir regardless of thedry-etching apparatus and the ashing apparatus will be described withreference to FIGS. 12 to 16. First, as depicted in FIG. 12, aninsulating film 32 such as a silicon oxide film or an SiOC film isformed on the barrier insulating film 29 so as to have a thickness of100 nm to 400 nm. Thereafter, photo-resist films are sequentially formedon the insulating film 32 and then patterned by exposure to form aphoto-resist pattern 33. At the time of the formation of such areservoir layer, in order to further increase the accuracy, a reflectionpreventive film can be used on a lower portion of the photo-resist filmsand an upper portion of the insulating film 32.

Next, as depicted in FIG. 13, the insulating film 32 is etched withusing the photo-resist pattern 33 as a mask, and etching is stopped onceon the barrier insulating film 29. Here, ashing is performed as depictedin FIG. 14 to remove the photo-resist pattern 33. By this means, theformation of a Cu residual film re-sputtered on the resist side wall canbe prevented. Thereafter, as depicted in FIGS. 15A and 15B, theinsulating films 29, 22, 21 and 20 are etched with using the insulatingfilm 32 as a mask. Then, after post-cleaning and a hydrogen annealingprocess are performed, the barrier insulating film 31 with a thicknessof 20 nm to 50 nm is formed so as to cover the upper surface and sidesurface of the second layer wirings 26, the barrier insulating film 29for use in the formation of a reservoir, and the insulating film 17.Through the process as described above, the wiring structure equivalentto that of FIGS. 10A and 10B can be achieved as depicted in FIGS. 16Aand 16B. Also, the wiring structure similar to that in FIGS. 11A and 11Bcan be obtained by using the formation method described above.

FIGS. 17A and 17B are cross-sectional views of principal parts in themanufacturing process of a semiconductor device according to stillanother embodiment of the present invention. In this still anotherembodiment, when the patterned insulating film 32 is used to etch theinsulating films 22, 21 and 20, if a selectivity between the insulatingfilm 32 and the barrier insulating film 29 is low, after the barrierinsulating film 29 is completely removed, a new barrier insulating film34 is formed on the insulating film 22, the second layer wirings 26 andthe insulating film 17 as depicted in FIGS. 18A and 18B. The barrierinsulating film 34 is made of, for example, a silicon nitride film, andit functions as a barrier insulating film for copper wirings. Therefore,the barrier insulating film 34 suppresses or prevents copper in the mainconductive film 26 b of each of the second layer wirings 26 from beingdiffused into the interlayer insulating film 36 formed later. As anothermaterial for the barrier insulating film 34, a single-element film ofany one of a silicon carbide (SiC) film, a silicon carbonitride (SiCN)film, and a silicon oxynitride (SiON) film may be used. When any ofthese films is used, the dielectric constant can be significantlyreduced compared with a silicon nitride film, and therefore, the wiringcapacitance can be reduced and the operation speed of the semiconductordevice can be improved. An example of the silicon carbide film formed byplasma CVD is BLOk (manufactured by AMAT), and its film formation gas isas described above. For the formation of the SiCN film, for example,mixed gas of helium (He), ammonium (NH₃) and trimethylsilane (3MS) isused. Also, an example of the silicon oxynitride film formed by plasmaCVD is PE-TMS (manufactured by Canon, relative permittivity=3.9). Forthe formation of the silicon oxynitride film, for example, mixed gas oftrimethoxysilane (TMS) gas and nitrogen oxide (N₂O) gas is used.

FIG. 19 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to theembodiment of the present invention continued from FIGS. 10A and 10B orFIGS. 16A and 16B. Insulating films 36 and 37 are formed on the barrierinsulating film 31. A Low-K insulating film such as SiOF or SiOC is usedfor the insulating film 36, and a silicon oxide film or the like is usedfor the insulating film 37 as a cap of the Low-K insulating film.Alternatively, for the simplification of the process, a single-elementfilm of silicon oxide or SiOC can be used for the insulating film 36 byomitting the insulating film 37.

In the present embodiment, the insulating film 36 is formed under thecondition that the insulating film 36 is not formed in a conformalmanner in a space between nearest wirings (minimum space betweenadjacent wirings or minimum pitch between wirings). Here, the nearestwirings correspond to the adjacent wirings having the minimum spacetherebetween in the wirings of the same layer (distance between adjacentwirings). In the space between nearest wirings, the reduction inparasite capacitance is more important.

In the space between nearest wirings, as the deposition of theinsulating film 36 proceeds, the reactive species is obstructed by adeposited matter near an upper portion of the side surfaces of thefacing wirings (facing surfaces of wirings), and gradually becomesdifficult to enter a lower portion thereof. For this reason, thedeposition rate near the lower portion of the side surfaces of thefacing wirings is lower than the deposition rate near the upper portionthereof. Therefore, the thickness of the insulating film 36 deposited onthe side surfaces of the facing wirings is not uniform, and thethickness near the upper portion is larger than the thickness near thelower portion. This phenomenon is more conspicuous in a space betweennearest wirings among the second layer wirings 26.

Therefore, in the space between nearest wirings of the second layerwirings 26, the insulating film 36 does not have a conformal shapereflecting the shape of the second layer wirings 26, and it has a gap(air gap) 35 as depicted in FIG. 19. Also, plasma CVD or the like can beused for the formation of the insulating film 36, and by adjustingconditions of forming the insulating film 36, the above-described gap(air gap) 35 can be easily formed in the space between nearest wirings.Furthermore, in the present embodiment, since the upper surface and sidesurface of the second layer wirings 26 are covered with the barrierinsulating film 31, the second layer wirings 26 can be formed only bythe main conductive film 26 b made of copper by omitting the conductivebarrier film 26 a in the second layer wiring 26. After the insulatingfilms 36 and 37 are formed, interlayer CMP is performed for theplanarization in order to remove the difference in level betweenwirings.

Next, after an insulating film 39 is formed as depicted in FIG. 20, areflection preventive film 40 and a photo-resist film are sequentiallyformed on the insulating film 39, and the photo-resist film is patternedby exposure to form a photo-resist pattern 41. Then, by the dry-etchingusing the photo-resist pattern 41 as a mask, the reflection preventivefilm 40 and the insulating film 39 are selectively removed, and thenashing is performed to remove the reflection preventive film 40 and thephoto-resist film. As a result, openings 42 to be wiring trenches latercan be fabricated as depicted in FIG. 21.

Next, patterning for forming through holes is performed. As depicted inFIG. 22, a reflection preventive film 43 and a photo-resist film aresequentially formed on the insulating films 37 and 39, and thephoto-resist film is patterned by exposure to form a photo-resistpattern 44. FIG. 23 is a plan view of principal parts in a regioncorresponding to FIG. 2 in the manufacturing process of a semiconductordevice continued from FIG. 22. FIG. 23 depicts second layer wiringpositions 26 c, a misaligned through hole position 38 connected to thesecond layer wirings and third layer wirings, and a reservoir formationposition 28 formed around the second layer wirings. Here, the positionof the through hole 38 actually misaligned at the time of the exposureof a via pattern of FIG. 21 is depicted.

FIG. 24 is a cross-sectional view of an A-A line in FIG. 23 continuedfrom FIG. 23. By the dry-etching using the photo-resist pattern 44 as anetching mask, the reflection preventive film 43 and the insulating films39, 37 and 36 are selectively removed, and ashing is performed to removethe reflection preventive film and the photo-resist films, therebyforming through-hole openings 45.

Next, as depicted in FIG. 25, trench process is performed with using theinsulating film 39 as a mask to fabricate trench openings 46.Subsequently, as depicted in FIG. 26, the barrier insulating films 29and 31 on the lower portion of the through holes are simultaneouslyremoved together with the insulating film 39 used as a mask.

Next, a thin conductive barrier film (first conductive film) 47 a madeof, for example, titanium nitride (TiN) or the like and having athickness of approximately 5 nm to 50 nm is formed by using sputteringover the entire main surface of the substrate 1. Other than titaniumnitride, various materials as those described above for the conductivebarrier film 26 a can be applied to the conductive barrier film 47 a.Subsequently, a relatively-thick main conductive film (second conductivefilm) 47 b having a thickness of, for example, approximately 800 nm to1600 nm and made of copper is formed on the conductive barrier film 47a. The main conductive film 47 b can be formed by using, for example,CVD, sputtering, or plating. Thereafter, the substrate 1 is subjected toa heat treatment in a non-oxidation atmosphere (for example, hydrogenatmosphere or nitrogen atmosphere) at, for example, approximately 150 to400° C. to reflow the main conductive film 47 b, thereby tightly fillingthe wiring trenches 45 and 46 with copper.

Next, the main conductive film 47 b and the conductive barrier film 47 aare polished by CMP. By this means, as depicted in FIG. 27, third layerwirings (wirings) 47 formed of the relatively-thin conductive barrierfilm 47 a and the relatively-thick main conductive film 47 b are formedin the wiring trenches 45 and 46. These third layer wirings 47 areelectrically connected to the first layer wirings 15 and the secondlayer wirings 26 via the through holes 45.

FIG. 28 is a plan view of principal parts corresponding to FIG. 2 in themanufacturing process of a semiconductor device continued from FIG. 27.FIG. 28 depicts the third layer wirings 47 and a formation position 49of a through hole connected to the second layer wiring and an upperlayer. Similar to the description of FIG. 7, as the measures for themisaligned through hole (misalignment of the through hole), a reservoirformation position 50 is set so that a limited portion of the thirdlayer wiring is in the same state as that of a normal interlayerstructure.

FIG. 29 is a cross-sectional view of an A-A line in FIG. 28 continuedfrom FIG. 28. Also in FIG. 29, the illustration of the portionscorresponding to the structure below the insulating film 17 in FIG. 3 isomitted. A barrier insulating film 48 having a thickness of 20 nm to 50nm is formed on the insulating film 37 and the third layer wirings 47.The barrier insulating film 48 is made of, for example, a siliconnitride film, and it functions as a barrier insulating film for copperwirings. Therefore, the barrier insulating film 48 suppresses orprevents copper in the main conductive film 47 b of the third layerwirings 47 from being diffused into an interlayer insulating film 53formed later. As another material for the barrier insulating film 48,for example, a single-element film of any one of a silicon carbide (SiC)film, a silicon carbonitride (SiCN) film and a silicon oxynitride (SiON)film may be used. When any of these films is used, the dielectricconstant can be significantly reduced compared with a silicon nitridefilm, and therefore, wiring capacitance can be reduced, and theoperation speed of the semiconductor device can be improved. Afabrication method thereof is identical to that described for theinsulating film 29 with reference to FIG. 8 and is therefore omitted.

Next, in the same manner as that described with reference to FIGS. 7 to11, a reservoir 50 is formed around the third layer wiring 47. Asdepicted in FIG. 30, after the barrier insulating film 48 and theinsulating films 37 and 36 are etched with using a resist mask pattern,a new barrier insulating film 51 with a thickness of 20 nm to 50 nm isformed on upper portions and side surfaces of the insulating films 36and 37, the barrier insulating film 48 and the third layer wirings 47.The barrier insulating film 51 is made of, for example, a siliconnitride film, and it functions as a barrier insulating film for copperwirings. Therefore, the barrier insulating film 51 suppresses orprevents copper in the main conductive film 47 b of the third layerwirings 47 from being diffused into the interlayer insulating film 53formed later. As another material for the barrier insulating film 51,for example, a single-element film of any one of a silicon carbide (SiC)film, a silicon carbonitride (SiCN) film and a silicon oxynitride (SiON)film may be used. When any of these films is used, the dielectricconstant can be significantly reduced compared with a silicon nitridefilm, and therefore, wiring capacitance can be reduced, and theoperation speed of the semiconductor device can be improved. Afabrication method is identical to that described for the insulatingfilm 29 with reference to FIG. 8 and is therefore omitted.

Next, as depicted in FIG. 31, insulating films 53 and 54 are formed andare then planarized by CMP. When upper layers are continuously formed,upper-layer wirings of fourth and further layer wirings can be formed byrepeating the method depicted in FIGS. 20 to 31. Also, the first layerwirings 15 can be copper wirings formed in the same manner as that ofthe second layer wirings 26, and the second layer wirings 26 can becopper wirings formed in the same manner as that of the third layerwirings 47.

According to the present embodiment, no CMP surface (surface polished byCMP) is present between the wirings of the same layer. Morespecifically, most of the insulating films 21 and 22 and the insulatingfilms 36 and 37 polished in the CMP process for forming the second layerwirings 26 and the third layer wirings 47 are removed, and the barrierinsulating films 31 and 51 are formed so as to cover the second layerwirings 26 and the third layer wirings 47. Therefore, in the secondlayer wirings 26 and the third layer wirings 47, other than the limitedreservoir region, the upper surfaces of the wirings of the same layerare not connected to each other via the CMP surface. Accordingly, thedielectric withstand voltage between wirings can be improved, and TDDBlife can also be increased. In other words, reliability of thesemiconductor device can be enhanced.

Also, gaps (air gaps) 35 and 52 are formed in spaces between nearestwirings in the wirings of the same layer where the capacitance reductionis needed most, and the barrier insulating film on the space betweennearest wirings, that is, on the bottom of the gap is thinner than thebarrier insulating film on the wirings. Therefore, the inter-wiringcapacitance can be efficiently reduced. Even when a material with arelatively high dielectric constant is used for the barrier insulatingfilms 31 and 51 on the wirings, the inter-wiring capacitance can bereduced. Also, in a region where a distance between adjacent wirings ofthe same layer is long, a Low-K material is formed without forming anair gap between wirings. Therefore, the entire mechanical strength canbe maintained.

In the present embodiment, insulating-film regions of the reservoirs 28and 50 are formed around a through hole and a portion connected to itslower layer wirings. However, since the ratio thereof is small withrespect to the region of the nearest wiring patterns, a capacitancereduction effect by the air gaps can be sufficiently achieved.

Furthermore, in the present embodiment, the air gap 35 or 52 may beformed not only in a space between the nearest wirings but also betweenadjacent wirings having a relatively short distance therebetween andwhose parasite capacitance therebetween is desired to be reduced.Conditions of an inter-wiring distance for forming an air gap can becontrolled by adjusting film-formation conditions of the barrierinsulating films 31 and 51 and film-formation conditions of theinsulating films 36 and 52. By this means, the inter-wiring capacitancecan be reduced by forming air gaps between adjacent wirings in a regionwhere the wiring pattern density is high, and mechanical strength can bemaintained by filling the spaces between wirings with a Low-K materialin a region where the wiring pattern density is low.

The inventor studied a capacitance reduction effect of the wiringstructure of the present embodiment through experiments and simulations.As a comparison example, a Low-K material was used for an insulatingfilm and an interlayer insulating film for filling the spaces betweenwirings, and a copper wiring structure formed by a normal Damascenetechnique was used.

As a result, the wiring structure of the present embodiment was able toreduce the inter-wiring capacitance by approximately 30% to 45% withrespect to the comparison example (conventional Damascene structure) andby approximately 10% to 15% with respect to the example of theconventional air-gap wiring (Patent Document 1) without increasing thenumber of processes. Also, the capacitance between an upper layer wiringand a lower layer wiring was hardly changed, and only the inter-wiringcapacitance of the same layer was decreased. Therefore, an influence ofwiring crosstalk can be reduced. Furthermore, an effective dielectricconstant εr (in the copper wiring structure of the comparison exampleabove, εr is approximately 3.1) was able to be significantly reduced toapproximately 2.3 to 2.7. Therefore, a low-capacitance wiring structureof the next and subsequent generations can be achieved with using theLow-K material of the same generation for the interlayer insulatingfilm.

Second Embodiment

FIG. 32 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to a secondembodiment of the present invention. The semiconductor device of thepresent embodiment has a multilayer wiring structure where the structurehaving a wiring layer and a reservoir in which air gaps are formedbetween adjacent wirings and these adjacent wirings are not connectedvia a CMP surface like the second layer wirings 26 and the third layerwirings 47 of the first embodiment and a wiring layer formed by using ageneral buried wiring technique are combined. In FIG. 31, up to theprocess of forming an insulating film 60 on an upper portion of fourthlayer wirings 55, the manufacturing process is almost similar to thosedescribed with reference to FIGS. 4 to 10 and FIGS. 18 to 30 of thefirst embodiment, and therefore, the description thereof is omitted andthe subsequent manufacturing process will be described here.

Fifth and subsequent wiring layers are formed by using a general buriedwiring technique, for example, a general Dual Damascene technique.First, after an insulating film 60 is planarized by CMP, fifth layerwirings are formed. That is, by using a Dual Damascene technique, fifthlayer wirings 61 buried in wiring trenches formed in the insulatingfilms 60, 59, 57 and 56 are formed. Then, on the insulating film 60including upper surfaces of the fifth layer wirings 61, an insulatingfilm 62 made of a silicon nitride film, a silicon carbide film, asilicon carbonitride film or a silicon oxynitride film is formed as abarrier insulating film. Thereafter, insulating films 63 and 64 made ofa Low-K material or the like are formed on the insulating film 62.Similarly, by using a Dual Damascene technique, sixth layer wirings 65buried in wiring trenches formed in the insulating films 62 to 64 areformed. Then, an insulating film 66 made of the same material as that ofthe insulating film 62, for example, silicon nitride is formed as abarrier insulating film on the insulating film 64 including uppersurfaces of the sixth layer wirings 65.

Note that a film formed by using CVD, for example, a silicon oxide film,an FSG (SiOF-based material) film, an SiOC film or a porous silicon(Polus-Si) material film can be used as each of the insulating films 36,53, 59 and 63.

In the multilayer wiring structure, in a wiring layer with arelatively-small space between adjacent wirings, that is, arelatively-small wiring pitch, the inter-wiring capacitance tends to beincreased and TDDB life tends to be decreased. According to the presentembodiment, in such a wiring layer where the inter-wiring capacitancetends to be increased and TDDB life tends to be decreased, no CMPsurface is provided between wirings of the same layer other than thelimited reservoir region, thereby increasing the TDDB life. Also, whilekeeping even a misaligned via contact in a proper state by using thereservoir structure, the inter-wiring capacitance can be reduced byforming an air gap in a space between nearest wirings in the wirings ofthe same layer.

Third Embodiment

FIG. 33 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to a thirdembodiment of the present invention continued from FIG. 3. Also in FIG.33, the illustration of portions corresponding to the structure belowthe insulating film 17 in FIG. 3 is omitted.

The present embodiment discloses air-gap wirings whose capacitancevariations are more reduced than those of the air-gap wirings describedin the first embodiment by using a via interlayer insulating film madeof a material different from a wiring interlayer insulating film as anetching stopper.

FIGS. 33 to 35 are cross-sectional views of principal parts in themanufacturing process of a semiconductor device continued from FIG. 2.

First, in the present embodiment, as depicted in FIG. 33A, an insulatingfilm 67 is formed on the insulating film 17 having the through holes 18embedded therein. For the insulating film 67, a Low-K material or aninsulating film, for example, an organic film such as a SiLK film isused. Also, as depicted in FIG. 33B, in view of mechanical protectionagainst CMP, for example, a silicon oxide film or an SiOC film may beused as an insulating film 68 formed as a cap on the insulating film 67.

Next, a reflection preventive film 69 and a photo-resist film aresequentially formed on the insulating film 67 or the insulating film 68,and then, the photo-resist film is patterned by exposure to form aphoto-resist pattern 70. Then, by the dry-etching using the photo-resistpattern 70 as an etching mask, the reflection preventive film 69 isselectively removed. Thereafter, by the dry-etching using thephoto-resist pattern 70 as an etching mask, the insulating films 68 and67 are selectively removed to form openings. Then, the photo-resistpattern 70 and the reflection preventive film 69 are subjected to ashingand removed. In this manner, as depicted in FIGS. 34A and 34B, openingsor wiring trenches 71 are formed. From the bottom surfaces of the wiringtrenches 71, the upper surfaces of the plugs 18 are exposed.

Next, as depicted in FIGS. 35A and 35B, a thin conductive barrier film(first conductive film) 72 a made of titanium nitride (TiN) or the likeand having a thickness of approximately 5 nm to 50 nm is formed over theentire main surface of the substrate 1 by using sputtering. Theconductive barrier film 72 a has functions of, for example, preventingthe diffusion of copper for forming a main conductive film describedfurther below and improving wettability of copper at the time of reflowof the main conductive film. As a material for the conductive barrierfilm 72 a, a high-melting metal nitride such as tungsten nitride (WN) ortantalum nitride (TaN) which hardly reacts with copper can be used inplace of titanium nitride. Also, as a material for the conductivebarrier film 72 a, a material obtained by adding silicon (Si) to ahigh-melting metal nitride, a high-melting metal unlikely to react withcopper such as tantalum (Ta), titanium (Ti), tungsten (W) or titaniumtungsten (TiW) alloy, and a TaN/Ta stacked barrier obtained by combiningTaN with high adhesion to an insulating film and Ta with high Cuwettability can be used.

Subsequently, a relatively-thick main conductive film (second conductivefilm) 72 b having a thickness of, for example, approximately 800 nm to1600 nm and made of copper is formed on the conductive barrier film 72a. The main conductive film 72 b can be formed by using, for example,CVD, sputtering, or plating. Thereafter, the substrate 1 is subjected toa heat treatment in a non-oxidation atmosphere (for example, hydrogenatmosphere or nitrogen atmosphere) at, for example, approximately 150 to400° C. to reflow the main conductive film 72 b, thereby tightly fillingthe wiring trenches 72 with copper.

Next, the main conductive film 72 b and the conductive barrier film 72 aare polished by CMP. By this means, as depicted in FIG. 35, second layerwirings (wirings) 72 formed of the relatively-thin conductive barrierfilm 72 a and the relatively-thick main conductive film 72 b are formedin the wiring trenches 71. These second layer wirings 72 areelectrically connected to the first layer wirings 15 via the plugs 18.

FIG. 36 depicts a wiring structure formed in the same manner as thatdescribed with reference to FIGS. 7 to 11. The insulating film 67 isleft at the reservoir position, and the insulating film 67 other thanthat position is removed. At this time, for the removal of an organicfilm, reducing etching gas is used. Therefore, the plasma CVD film 17serves as an etching stopper, and the depth for removal becomes uniformcompared with the case of time-controlled etching. Accordingly, theshape of the gaps to be formed later becomes uniform, and capacitancevariations can be reduced more compared with the air-gap wiringsdisclosed in Patent Documents 1 and 2. As described in the firstembodiment, capacitance can be reduced by forming the barrier insulatingfilm 74 so as to have a smaller thickness at a portion between thenearest wirings than that on the wiring 72.

Next, as depicted in FIGS. 37A and 37B, an insulating film 76 is formedon the barrier insulating film 74 by using plasma CVD in the same manneras that depicted in FIG. 19 to form gaps 75. Then, after planarizing theinsulating film 76, an insulating film 77 is formed. At this time,similar to the formation described with reference to FIGS. 35 and 36,the insulating film 76 is assumed to be a plasma CVD film such as SiO2,SiOF or SiOC, and the insulating film 77 is assumed to be an organicfilm. By stacking the films in this manner, the insulating film 76serves as an etch stopper when the insulating film 77 is removed, and auniform gap height can be obtained and capacitance variations can bereduced.

The film thickness of the insulating film 76 is set to a position deeperthan the wiring bottom of the third layer wirings 79 formed later. Bythis means, capacitance variations can be reduced, and at the same time,capacitance itself can be further reduced.

Also, as depicted in FIG. 37B, an insulating film 78 may be used as aCMP protective film for use in the formation of the third layer wirings79 described further below.

Next, the third layer wirings 79 are formed by using a Dual Damascenetechnique in the same manner as the formation method depicted in FIGS.20 to 27.

FIG. 39 depicts a wiring structure after the insulating film 77 in FIG.38A and the insulating film 77 and insulating film 78 in FIG. 38B areremoved. Similar to the case of FIG. 36, the insulating film 77 which isan organic film is removed with the reducing etching gas, and therefore,the insulating film 76 which is a plasma CVD film serves as an etchstopper and the insulating film 77 is left on a lower portion of thethird layer wirings 79. In FIG. 39, in order to reduce capacitancevariations and further reduce capacitance itself at the same time, theetching depth of the insulating film 77 is characteristically lower thanthe bottom of the third layer wirings.

Next, in the same manner as the case of FIGS. 7 to 11, a barrierinsulating film 80 and a barrier insulating film 81 are formed on thethird layer wirings 79. At this time, by setting a condition such thatthe barrier insulating film 81 is not conformal, the film thickness at aportion between nearest wirings is formed smaller than the filmthickness on the third layer wirings 79, so that capacitance can bereduced.

FIG. 40A depicts a wiring structure formed in the same manner as that ofthe case of FIGS. 37A and 37B. Gaps 82 are formed while forming aninsulating film 83, and a plasma CVD film such as SiO2, SiOF or SiOC isadopted to the insulating film 83. Thereafter, an insulating film 84which is an organic film is formed. As depicted in FIG. 40B, aninsulating film 85 may be used as a CMP protective film.

Fourth Embodiment

FIG. 41 is a cross-sectional view of principal parts in themanufacturing process of a semiconductor device according to a fourthembodiment of the present invention. The semiconductor device of thepresent embodiment has a multilayer wiring structure where the structurehaving a wiring layer and a reservoir in which air gaps are formedbetween adjacent wirings and these adjacent wirings are not connectedvia a CMP surface like the second layer wirings 72 and the third layerwirings 79 of the third embodiment and a wiring layer formed by using ageneral buried wiring technique are combined. In FIG. 41, up to theprocess of forming an insulating film 87 on an upper portion of a fourthlayer wiring 85, the manufacturing process is almost similar to thosedescribed with reference to FIGS. 37 to 40 of the second embodiment, andtherefore, the description thereof is omitted and the subsequentmanufacturing process will be described here.

Fifth and subsequent wiring layers are formed by using a general buriedwiring technique, for example, a general Dual Damascene technique.First, after an insulating film 90 is planarized by CMP, fifth layerwirings are formed. Then, by using a Dual Damascene technique, fifthlayer wirings 91 buried in wiring trenches formed in the insulatingfilms 90, 89, 87 and 86 are formed. Then, on the insulating film 90including upper surfaces of the fifth layer wirings 91, an insulatingfilm 92 made of a silicon nitride film, a silicon carbide film, asilicon carbonitride film or a silicon oxynitride film is formed as abarrier insulating film. Thereafter, insulating films 93 and 94 made ofa Low-K material or the like are formed on the insulating film 92.Similarly, by using a Dual Damascene technique, sixth layer wirings 95buried in wiring trenches formed in the insulating films 92 to 94 areformed. Then, an insulating film 96 made of the same material as that ofthe insulating film 92, for example, silicon nitride is formed as abarrier insulating film on the insulating film 94 including uppersurfaces of the sixth layer wirings 95.

Note that a film formed by using CVD, for example, a silicon oxide film,an FSG (SiOF-based material) film, an SiOC film or a porous silicon(Polus-Si) material film can be used as each of the insulating films 76,83, 89 and 93.

In the multilayer wiring structure, in a wiring layer with arelatively-small space between adjacent wirings, that is, arelatively-small wiring pitch, the inter-wiring capacitance tends to beincreased and TDDB life tends to be decreased. According to the presentembodiment, in such a wiring layer where the inter-wiring capacitancetends to be increased and TDDB life tends to be decreased, no CMPsurface is provided between wirings of the same layer other than thelimited reservoir region, thereby increasing the TDDB life. Also, whilekeeping even a misaligned via contact in a proper state by using thereservoir structure, the inter-wiring capacitance can be reduced byforming an air gap in a space between nearest wirings in the wirings ofthe same layer.

1-13. (canceled)
 14. A manufacturing method of a semiconductor devicecomprising the steps of: (a′) forming a plurality of wiring trenches ina first insulating film and a second insulating film on a semiconductorsubstrate; (b′) forming a first conductive film on the second insulatingfilm including respective insides of the plurality of wiring trenches;(c′) forming wirings formed of the first conductive film inside therespective wiring trenches by removing a portion of the first conductivefilm outside the wiring trenches by CMP; (d′) forming a first barrierinsulating film on the second insulating film and the wirings; (e′)forming a reservoir position by removing the first barrier insulatingfilm and the second insulating film except portions of the first barrierinsulating film and the second insulating film in lower regions andtheir peripheral regions of through holes, which are formed later andfrom which upper surfaces of the wirings are exposed; (f) forming asecond barrier insulating film on the first barrier insulating film andside and upper surfaces of the wirings so that the second barrierinsulating film on spaces between the wirings is made thinner than thesecond barrier insulating film on the wirings; (g′) forming a thirdinsulating film on the second barrier insulating film while leaving gapsin space regions between the wirings from which the first barrierinsulating film and the second insulating film have been removed; (h′)forming through holes penetrating through the first barrier insulatingfilm, the second barrier insulating film and the third insulating filmon an upper portion of the wirings; and (i) forming a second conductivefilm inside the through holes.
 15. The manufacturing method of thesemiconductor device according to claim 14, wherein the second barrierinsulating film is not formed on the spaces between the wirings.
 16. Themanufacturing method of the semiconductor device according to claim 14,wherein depth of each of the wiring trenches is formed upper than aninterface between the first insulating film and the second insulatingfilm, and the second insulating film is removed up to an upper surfaceof the first insulting film.
 17. The manufacturing method of thesemiconductor device according to claim 14, wherein the first conductivefilm is formed by depositing a first conductive barrier film on thefirst insulating film, and then depositing a main conductive film madeof copper on the first conductive barrier film.
 18. The manufacturingmethod of the semiconductor device according to claim 17, wherein thefirst conductive barrier film is any one of a high-melting metal nitridefilm, a high-melting metal film, and a stacked film thereof. 19-26.(canceled)